Development of an Automated Storage of Numerical Simulation Results Based on OpenBIS

Tommy Weber, Research Assistant, 01.06.2023-30.11.2023

Storage and documentation of simulation data is fundamental. Therefore, an automated storage system for simulation data is wanted in combination with a database. The first phase of the project combines two systems:

  1. Storage system (E.g. OpenBIS,, incl. data storage, versioning, and SQL database
  2. Providing interface to internal simulation tools of the TET institute (, by a python wrapper. Primary focus is on CONMLS. However, the possibility to connect other tools is to be considered e.g. CONCEPT-II, CONMTL.

The first phase has an environment as result which enables to define experiments. An experiment can be e.g. a printed circuit board (PCB) (layers, ports, vias, …). Within the experiment simulations are performed with respect to variations of specified parameters (e.g. geometry of the PCB). Data points are sampled based on a random, latin hypercube, or active sampling. Simulation results are stored as scattering parameters on the storage system. Simulation results and setups can be retrieved fully from the storage system. At the end of phase one the functionality should be provided for internal use in the institute of electromagnetic theory.

High Speed Automotive Interconnect Design for Gbps Links

High-speed interconnect design for wired links in digital systems has been a well-established field of research and innovation for several decades now. In contrast, automotive high-speed interconnects have only recently advanced to higher and higher data rates. Correspondingly, models for components specific to automotive interconnects have not been created or validated to a large extent nor has a sufficient model-to-hardware correlation been established. In addition, automotive high-speed interconnects must fulfill strict requirements regarding electromagnetic compatibility (EMC) regulations. This project aims to develop high-speed interconnect models used in automotive applications on a system level. These models will be adapted to analyze printed circuit board (PCBs) stack-ups used in automotive applications in combination with assembly and interconnection technologies (AITs) and provide insight of the Signal Integrity performance of high-speed links in harsh automotive environmental standards to have a functional system which fulfill the electrical performance as well as reliability requirements.

Multilayered PCB Stack-Up used in an Automatve Application.

Extracted Insertion Loss of a Transmission Line using a Delta-L Deembedding Algorithm. Conductor Loss and Dielectric Loss are extracted via the Curve-Fitted Insertion Loss of the DUT.

Funding: Robert Bosch GmbH
Contact: Jose Enrique Hernandez Bonilla
Start date: 01.09.2022

Research and Modelling of Ultra-High-Speed Interconects

The expansion of information networks such as the industrial Internet of Things (IoT) is creating an ever-increasing demand for data. This logically generates a demand for data generation, processing, storage and data transport between these steps. This project is investigating ways to ensure fast data transport. The goal is to model “Ultra-High-Speed Interconnects” that enable data transmission of more than 100 Gbps per data link. These links usually consist of two components. One is the physical channel and the other is an I/O structure. In addition, challenges arise in the form of losses due to the materials used and other disturbances that must also be taken into account. Among other things, the influence of different equalization will be investigated and adapted to physical models of the channel. For this purpose, it is planned to use machine learning methods, e.g. to be able to make predictions about possible design parameters for these Ultra-High-Speed Interconnects.

Schematic drawing of a connection between two microchips across a backplane.

CST simulation results for a structure consisting of two vias connected to each other by a stripline.

Funding: Freie und Hansestadt Hamburg
Contact: Til Hillebrecht, M.Sc.
Start date: 17.10.2022

Electronic Design Flow Improvement with Machine Learning Tools

The design of modern printed circuit boards (PCBs) is a challenging task and requires the compliance with a variety of specifications. To reduce the risk of a poor design and getting the desired functionality, the design processs is accompanied by many electromagnetic simulations. In combination with the time requirement of an individual simulaion this results in a large effort which needs a lot of computational resources. Because future designs will have a higher complexity and larger integration level, decreasing the time requirement for an individual simulation is an important task to solve. Without improving the simulation mechanism the design ow will require more time which results in additional costs for the development. This project aims to improve the design ow by providing a more efficient design tool and process. In the area of machine learning algorithms some promising ideas are found. Publications in recent years provide methods to increase the efficiency of optimization processes – for example generic algorithms for the placement of decoupling capacitors. With artificial neural networks first results are achieved by investigating the impedance of the power delivery network under the in uence of decoupling capacitors. Future work shall increase the applicability of artificial neural networks to a wider range of simulation tasks. Therefore different aspects have to be investigated. The focus is on printed circuit boards which are commonly used in many electronic devices. The functionality and capabilities of printed circuit boards is well understood. One of the most important aspects within this project is to provide not only a faster simulation ow but to ensure the consistency of simulation results with existing tools and methods.

Typical multilayer printed circuit board with four layers. Two layers are for the power supply and two layers are for the signal transmission. By placing decoupling capacitors on the PCB the impedance of the power delivery network shall be improved. Multiple parameters (material constants and dimensions) are influencing
the eletrical behavior of the PCB.

The target impedance is violated by the impedance of the power delivery network, thereby the design is not sufficient. This fact can either be taken from a conventional simulations tool or with an artificial neural network. Using artificial neural networks is a promising idea. Depending on different input parameters (material constants and dimensions) predictions of the electrical behavior are made.

Funding: Freie und Hansestadt Hamburg
Contact: Morten Schierholz, M.Sc.
Start date: 01.10.2021

Application of Model Order Reduction Techniques to the Simulation of Complex Interconnect Systems

Interconnects in modern electronic systems constitute very dense and complex structures that demand highly efficient methodologies for their modeling and design. Even with semi-analytical or hybrid simulation approaches, the analysis of this type of systems often implies very large models and long execution times. This project, which is developed in collaboration with the Instituto Tecnológico de Costa Rica (ITCR), deals with the exploration of numerical techniques to facilitate the handling and processing of such complex models.

Different macromodeling techniques, such as vector fitting algorithms and matrix state representations, are being explored as an additional resource that can assist the handling, concatenation, and processing of interconnect models. Stochastic frequency-domain macromodels, combining the descriptor form representation for a dynamical system with the Polynomial Chaos Expansion technique, are also being analyzed. This will allow to include the variability analysis of the system for any frequency over a desired frequency range. To reduce the number of required samples, techniques for the analytical concatenation of macromodels in descriptor form will be adapted. Together with the use of semi-analytical techniques for the sample construction, this process should guarantee the accurate representation of complex multiport systems with different random input variables, within a short time. To evaluate the performance of these techniques, the comparison with purely numerical techniques will be addressed with realistic modeling scenarios.

Example of a Vector fitting approximation of an S-Parameter crosstalk model as a function of the number of poles.

Complex plane pole and zero constellation of a vector fitting (VF) macromodel as a function of the number of poles, extracted from a high-speed channel S-Parameter model.

Funding: Instituto Tecnologico de Costa Rica (ITCR)
Contact: Luis Ernesto Carrera Retana, M. Sc., Prof. Renato Rimolo-Donadio
Start date: 01.01.2017

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Evaluation of Interconnects up to 100 GHz Using Machine Learning

Ph. D. Thesis Katharina Scharff: 16.04.2016 – 15.10.2020

This thesis presents a contribution to the evaluation and modeling of high-speed electrical interconnects on printed circuit boards up to 100 GHz using machine learning. Parametric studies of different models are conducted with efficient numerical methods. The crosstalk is analyzed for different interconnect types. Machine learning methods are introduced as an alternative design method. They are evaluated regarding the reliability of the predictions and the necessary effort.

Data flow and concurrence of tools used in this study. Random jitter (RJ), sinusoidal jitter (SJ), as well as duty cycle distortion (DCD) are added as part of the transmitter as indicated. Furthermore, a voltage swing of 1V and a slew rate of 44 ps applies. (Source: TET, TUHH).

Tools bases on Machine Learning (ML) often show very short simulation times when compared to physics based tools for signal integrity applications – be them 2D/2.5D or fully 3D. They fall behind though in accuracy and flexibility. It all depends therefore on a smart usage of ML. (Source: TET, TUHH).

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Stochastic Contour Integral Methodology for the Computation of Two-Dimensional Electromagnetic Wave Propagation

David Dahl, DFG Project 01.08.2015 – 31.07.2018

The project will extend the so-called contour integral method (CIM) for the computation of two-dimensional packaging and interconnect structures such as printed circuit boards and planar optical substrates to take into account stochastic boundary conditions and simulation parameters. The stochastic contour integral method will be studied from a mathematical point of view, implemented in a numerically efficient way, and demonstrated with relevant application examples. To take into account stochastic boundary conditions and input parameters, the polynomial chaos expansion (PCE) known from other application areas will for the first time be applied in the context of a contour integral method for electrodynamics. For this purpose, a partially existing Fortran code will be extended by methods that can take into account statistical variations in the excitation as well as in the geometry and material parameters of the structure under investigation. On the one hand, a mathematical analysis of the stochastic contour integral methodology will be carried out, including demonstrations of the methodology with help of suitable examples and investigations with regard to the limitations of the numerical treatment. On the other hand, the methodology and the existing numerical code will be extended specifically for stochastic problems in the areas of microwave engineering and integrated planar optics. The potential of the methodology will be demonstrated by applying the extended code to structures that are relevant from an engineering point of view. By virtue of the cooperation between the Institute of Electromagnetic Theory and the Institute of Mathematics of the Hamburg University of Technology (TUHH) the project will facilitate fundamental research in mathematics and numerics in the context of a relevant and challenging application area in engineering.

The contour integral methods can be applied for the modeling of power distribution networks in printed circuit boards. The PCE can be used to study the influence of variations of the decoupling capacitor properties. (Source: TET, TUHH).

The contour integral method can be applied in planar optics for the efficient simulation of photonic crystals which can be used for building optical waveguides. (Source: TET, TUHH).

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Combined Assessment of Interconnect and Equalization in Data Links on Multilayer Printed Circuit Boards

Ph. D. Thesis Torsten Reuschel. 01.10.2013 – 15.10.2018

Increasing data rates and reduced design margins oppose a detailed consideration of the diverse aspects of high-speed digital links, such as the passive channel, equalization, and coding. This work offers novel methods for the computationally efficient design and validation of links. A combined system perspective is established based on predominant physical parameters of the interconnect and key parameters of equalizer design. This enables a systematic prediction of design constraints and is accompanied by a study of advanced uncertainty quantification methods for pre- and post-layout design.

Crosstalk distribution in large via-array at different frequencies. The simulation is carried out using the tool Multilayer Substrate Simulator, which is developed at the institute. (Source: TET, TUHH).

Exemplary interconnect between two large via-arrays. The striplines within the first cavity are indicated. The eye diagram is efficiently generated using statistical methods. (Source: TET, TUHH).

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Electromagnetic Modeling and Optimization of Through Silicon Vias

Ph. D. Thesis David Dahl. 01.10.2012 – 13.12.2017

This thesis presents the simulation and the design of vertical interconnects in silicon substrates known as through silicon vias (TSVs) which are applied as a component of 3D integration of integrated circuits. Numerical methods of comparably high efficiency are developed and applied in order to simulate the electromagnetic properties of large realistic arrays of TSVS. The proposed methods are correlated with alternative methods and parameter variations are carried out to derive design guidelines. Further, several test structures with TSV are developed and the measurement results are correlated with the results from electromagnetic simulations.

Schematic layout of a part of a silicon interposer where Through Silicon Vias (TSV) establish a connection between top and bottom of the structure. The metallic barrels of typically circular cross-section are electrically isolated from the conductive silicon substrate material by a thin silicon dioxide layer. Two principle types of wave propagation are investigated. (Source: TET, TUHH).

A physics-based via model assuming metallic boundaries on top and bottom of the interposer structure. The near field effects are modeled by lumped capacitances while wave propagation in the cavity constituted by the substrate and the enclosing metallic layers is represented by the “parallel plate impedance”. (Source: TET, TUHH).

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Software-Benchmarking for Signal and Power Integrity Applications

Industry Project. 01.03.2012 – 31.12.2014

The Institute of Electromagnetic Theory is evaluating SPEAG’s SEMCAD software, a FDTD based field solver, with respect to typical problems in signal and power integrity design of digital systems. Schmid & Partner Engineering AG (SPEAG) is a Zurich based company that develops and manufactures advanced numerical tools and instrumentation for evaluation of electromagnetic near- and far-fields from static to optical frequencies. SPEAG focuses on evaluation and optimization of EM fields in complex environments such as close to and within the human body. Typical applications include EM safety and design optimization of mobile phones, MRI, and medical implants.

Below is a benchmark from electronic packaging: A ball grid array (BGA) socket model consisting of approx. 28 million cells. Reflection, transmission, and crosstalk parameters were extracted in the frequency domain up to 40 GHz from time domain data. It can be seen that the crosstalk reaches a maximum in the frequency range from 10 to 15 GHz.

SEMCAD model of ball grid array socket.

S-parameters obtained from SEMCAD simulations.

A second benchmark is the silicon interposer below with a pair of through silicon vias (TSVs) consisting of about 1 million cells. Results from time domain simulation using two digital pulses for excitation are shown. It can be seen that the TSVs shows mostly inductive reflection and produce crosstalk during rise and fall times.

SEMCAD model of silicon interposer with through silicon vias.

Time domain results from SEMACD simulation.

50+ Gbps High Speed Serial Link Design for Digital Systems

Industry Project. 01.08.2014 – 31.10.2014

High speed serial link design for digital systems is rapidly approaching the 25-50 Gbps data rate and is likely to move beyond in the next decade as can be seen e.g. from the recent 56 Gbps Common Electrical Interface (CEI) initiative of the Optical Internetworking Forum (OIF). With the increase in data rate problems in the areas of signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC) will exacerbate and require more attention than before in order to achieve a system that is not threatened in its electrical integrity (see figure below).
In this research project the Institute of Electromagnetic Theory was investigating on behalf of HUAWEI Research Europe the state of the art, the technical issues, and the necessary steps for electrical integrity at such advanced data rates. Specifically the following research areas were addressed in detail

– basic elements of successful link design methodologies,
– necessary CAD tools for link design,
– specific problems and challenges at 50+ Gbps signaling,
– suitable packaging & interconnect structures for 50+ Gbps signaling,
– most important research areas in the near future.

The results were summarized in a White Paper and presented at HUAWEI.

The concept of electrical integrity for digital systems: Typically, three aspects of electrical integrity are distinguished (left): power integrity, signal integrity, and electromagnetic compatibility. Although the three aspects have different objectives and use different methodologies, they are closely interlinked. The schematic at the right side of the figure illustrates the target domains of the different aspects, which can roughly be described as follows: Power integrity is concerned with providing a noise free power supply, signal integrity is concerned with the quality of signal transmission, and the electromagnetic compatibility is concerned with mitigating electromagnetic interference.

Via Array Modeling for Application in Fast, Energy-Efficient Digital Systems

Ph. D. Thesis Sebastian Müller. 01.04.2010 – 31.07.2014

This thesis studies the application of physics-based via models for an efficient modeling of large via arrays in multiglayer PCBs. Three main aspects are addressed: the study and improvement of the modeling accuray, the study and improvement of the model efficiency, and the application of the model in a systematic evaluation of via array design alternatives for high speed links.

With regard to the modeling accuracy, the application of an improved local field model is identified as a suitable way to improve the model accuraxy for the simulation of via arrays, especially at frequencies above 20 GHz. With the improved model, an accurate simulation of via arrays with a pitch of 60 mil or larger becomes possible in the frequency range up to 50 GHz. Improvements with regard to the model efficiency lead to a reduction of calculation times which allows to carry out fast design explorations for smaller via arrays on a stadard PC. Finally, an approach for the systematic design ebaluation is presented which intefrates the adventages of the efficient physics-based via model in a larger concept. With the approach, a quantitative comparison of design alternatives bevomes possible that takes into account the impact of design changes on both signal integrity and energy efficiency for the complete system.

(Source: TET, TUHH).

(Source: TET, TUHH).

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Exploration of Power Supply Noise Effects on Maximum Data Rates of High Speed Digital Links in Advanced Server Systems

Industry Project. 18.06.2010 – 17.06.2013

High speed digital links in IBM’s server systems today are running at data rates of up to 10 Gigabit per second (Gbps). These links are crucial for the overall performance of the system and are carefully designed with respect to signal integrity and bit error rates. The design process follows an iterative procedure in which I/O circuit designers and package designers collectively optimize the link performance using appropriate models for each element of the communication system. As data rates increase in next generation platforms to exceed 12 Gbps, the fundamental noise coupling mechanisms will change making a localized nearest neighbour analysis less relevant. Newer architectures are also increasingly relying on differential links to provide a measure of noise rejection. Increasing data rates will involve new noise coupling mechanisms, many of which are increasingly sensitive to skew, power supply noise, and return current path discontinuities.

IBM Watson Supercomputer based on Power7 (Source: IBM)

Transistors on IBM Power6 Chip (Source: IBM)

The design process for high speed digital links is nowadays focused on the assessment of signal interconnect performance. Power delivery network design is usually a separate effort and its implications for signal quality and maximum achievable data rates are not routinely studied or accurately quantified. In this joint research project the Institute of Electromagnetic Theory in close collaboration with a team from IBM Germany Research & Development explored the effect of power supply noise on the maximum achievable data rates in IBM’s high speed digital links. The team developed successfully a power delivery model for packaging structures and a method for inclusion of simultaneous switching noise into the link budget simulation.

Simulated eye diagram for a high speed digital link.

Simulated eye diagram subject to power supply noise.

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Development, Validation and Application of Semi-Analytical Interconnect Models for Efficient Simulation of Multilayer Substrates

Ph. D. Thesis Renato Rimolo-Donadio. 01.11.2006 – 31.12.2010

This project deals with the efficient modeling and simulation of multilayer substrates in high-speed electronic systems.
Semi-analytical models for vias and traces in packages and printed circuit boards are proposed and incorporated into a framework for automatic simulation of multilayer structures. The models are validated with general-purpose numerical methods for electromagnetic simulation and measurements, using typical configurations such as differential and single-ended links. Application scenarios of realistic complexity for signal integrity, power integrity, and electromagnetic compatibility are evaluated and the co-simulation of these three domains is explored.

Illustration of interconnect levels in high-speed electronic systems. On-chip interconnects mainly consist of metallization layers of IC technologies, which are typically arranged as grid meshes. Off-chip interconnects cover the first (package and MCM), second (board), and third (motherboard/backplane) levels. Multilayer substrates are used to support the off-chip signal and power networks. (Source: TET, TUHH).

Functional block diagram of the modeling approach for simulation of multilayer substrates. The figure depicts the interrelation between the different model components. (Quelle: TET, TUHH).

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