SI/PI Database

The SI/PI-Database is a collection of printed circuit board (PCB) based structures which represent different electromagnetic aspects for signal integrity and power integrity applications. The structures have different components and interconnecting elements e.g. vias, via-arrays, power, ground planes. Each structures contains many variations of geometry and material parameters along with the simulation results. All structures were simulated with a physics-based approach which was cross validated with a full-wave solver for different structures.

Physics-Based Approach related publications:

An overview of the structures is given in the following table along with the simulated frequency range, variations of the geometry and materials and a general description of the structure. The structure explanation has all necessary information to rebuild the setup and verify the simulation results. Additionally classification labels are explained if available.
The SI/PI-Database is intended to help the development of machine learning tools and techniques for signal integrity, power integrity and electromagnetic compatibility applications. Without the need to create the data for the machine learning investigations a performance boost during the development of the techniques should be observed.

Any usage of the data of the SI/PI-Database has to be referenced to the following article:

M. SCHIERHOLZ, A. SANCHEZ-MASIS, A. CARMONA-CRUZ, X. DUAN, K. ROY, C. YANG, R. RIMOLO-DONADIO, C. SCHUSTER,
“SI/PI-Database of PCB-Based Interconnects for Machine Learning Applications”,
IEEE Access, vol. 9, pp. 34423-34432, 2021.

To get access to the data please fill out the contact form at the bottom. The download link will be provided by the entered e-mail address. You will receive an e-mail within 24 hours under normal circumstances with a download link for a zip-archive. The zip-archive contains multiple files. The description of the structure with the parameter variations is explained. A file which has all parameter variations along with classification labels and the simulation index (simu_index). The scattering parameters for the according simulation file is found by the (simu_index) . For each parameter variation with the a touchstone file simu_index.sNp is available.

Further benchmark problems related to electronic packaging are available in The Packaging Benchmark Suite by IEEE Electronics Packaging Society (EPS) Technical Committee on Electrical Design, Modeling and Simulation (TC-EDMS).

Name
Description No. of
Simulations
Size of
Compressed
Data Set
Detailed
Description
Image
8-Layer PCB based PDN with two Via Arrays Latin Hypercube SamplingA PCB setups with variations of the geometry and material are simulated with a physics-based via model. In the frequency spectrum of 1 MHz to 1 GHz 334 linear spaced frequency points are used. The PCB has two via arrays with varying positions. Overall the board has 28 ports and no components are attached. For the sampling the Latin Hypercube is applied.1000042 GBPDF

4-Layer PCB based PDN with two Via Arrays Random SamplingA PCB setups with variations of the geometry and material are simulated with a physics-based via model. In the frequency spectrum of 1 MHz to 1 GHz 334 linear spaced frequency points are used. The PCB has two via arrays with varying positions. Overall the board has 28 ports and no components are attached. The sampling is performed randomly.1000044 GBPDF

PWR/GND Plane PCB with 11x11 Via-ArrayThis structure contains a power delivery network (PDN) on a PCB with one cavity, a power plane on the bottom and a ground plane on top. One port is in the center of a via-array and is the port that is decoupled by placing decoupling capacitors (decaps) on the surrounding via array. At this port the impedance of the PDN is observed. The variations for this structure include changing the distance of the planes, the material properties and the decaps. For the decaps the location, capacitance and number was varied. The capacitors were chosen from a library containing overall 15 values including equivalent series resistance and equivalent series inductance.583991.3 GBPDF



Link on 11 Cavity PCB with two 10x10 Via-ArraysA link between two via-arrays was simulated. The stackup consists of 11 cavities with power and ground planes, including striplines to connect the via-arrays. 12 single ended ports are simulated. Variations are carried out for geometry and parameter.70312.4 GBPDF



Link on 8 Cavity PCB with two 10x10 Via-Arrays
A link between two via-arrays was simulated. The stackup consists of 8 cavities with power and ground planes, including striplines to connect the via-arrays. 12 single ended ports are simulated. Variations are carried out for geometry and parameter.70312.5 GBPDF


5x5 Via-Array on 10 Cavity PCBA 5×5 via array is located on a 10 cavity stackup. The connection of the GND and signal vias is shown, with a via ratio of 2 : 1 for signal and GND respectively. All planes of the stackup are connected by the GND vias. All signal vias have two ports, one at the top side and on at the bottom side of the PBC.500012.2 GBPDF


Link on 10 Cavity PCB with two 5x5 Via-ArraysThe structure has a link between two 5x5 via-arrays. Both arrays are located on the same multilayer stackup of 10 dielectric cavities. In the fifth cavity vias of both arrays are connected by striplines. GND vias connect all planes.150023.7 GBPDF



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