Signal and Power Integrity (SI/PI)

Combined Assessment of Interconnect and Equalization in Data Links
on Multilayer Printed Circuit Boards

Ph. D. Thesis Torsten Reuschel. 01.10.2013 – 15.10.2018

Increasing data rates and reduced design margins oppose a detailed consideration of the diverse aspects of high-speed digital links, such as the passive channel, equalization, and coding. This work offers novel methods for the computationally efficient design and validation of links. A combined system perspective is established based on predominant physical parameters of the interconnect and key parameters of equalizer design. This enables a systematic prediction of design constraints and is accompanied by a study of advanced uncertainty quantification methods for pre- and post-layout design.

Picture

Exemplary interconnect between two large via-arrays. The striplines within the first cavity are indicated. The eye diagram is efficiently generated using statistical methods. (Source: TET, TUHH).

Picture

Crosstalk distribution in large via-array at different frequencies. The simulation is carried out using the tool Multilayer Substrate Simulator, which is developed at the institute. (Source: TET, TUHH).

Related Publication:

Dr.-Ing. Torsten Reuschel
Combined Assessment of Interconnect and Equalization in Data Links on Multilayer Printed Circuit Boards
Ph. D. Thesis

Torben Wendt, Torsten Reuschel, Christian Schuster
Direct Prediction of Linear Equalization Coefficients Using Raised Cosine Pulse Shaping in Frequency Domain
22nd IEEE Workshop on Signal and Power Integrity SPI 2018, Mai, Brest, France

Torsten Reuschel, Ömer Yildiz, Jayaprakash Balachandran, Cristian Filip, Nitin Bhagwath, Bidyut Sen, Christian Schuster
Efficient Sensitivity-Aware Assessment of High-Speed Links Using PCE and Implications for COM
DesignCon, Santa Clara, CA, USA, Jan. 2018

Torsten Reuschel, Jan Birger Preibisch, Katharina Scharff, Renato Rimolo-Donadio, Xiaomin Duan, Young H. Kwark,
Christian Schuster
Efficient Prediction of Equalization Effort and Channel Performance for PCB-Based Data Links
IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 7, No. 11, 2017

Torsten Reuschel, Jan Birger Preibisch, Christian Schuster
Efficient Design of Continuous Time Linear Equalization for Loss Dominated Digital Links
IEEE Workshop on Signal and Power Integrity (SPI), Lake Maggiore (Baveno), Italy, May 7-10, 2017

Katharina Scharff, Torsten Reuschel, Xiaomin Duan, Heinz-Dietrich Brüns, Christian Schuster
Exploration of Differential Via Stub Effect Mitigation by Using PAM4 and PAM8 Line Coding
IEEE Workshop on Signal and Power Integrity (SPI), Lake Maggiore (Baveno), Italy, May 7-10, 2017

B.Rohrdantz, T.Jaschke, T.Reuschel, S.Radzijewski, A.F. Jacob,
An Electronically Scannable Reflector Antenna Using a Planar Active Array Feed at Ka-Band
IEEE Transactions on Microwave Theory and Techniques,vol. 65,no.5,pp.1650-1661, March, 2017

Yu Zhao, Rainer Grünheid, Gerhard Bauch, Torsten Reuschel, Christian Schuster
Redundant and Non-Redundant Spectrum Shaping Schemes for Reflection-Limited Chip-to-Chip Communication
International ITG Conference on Systems, Communication and Coding (SCC), Hamburg, Germany, February 6-9, 2017

Jan Birger Preibisch, Jayaprakash Balachandran, Torsten Reuschel, Katharina Scharff, Bidyut Sen,
Christian Schuster
Exploring Efficient Variability-Aware Analysis Method for High-Speed Digital Link Design Using PCE
UBM DesignCon Conference, Santa Clara, CA, USA, 31. Januar 31 – 2. February, 2017

David Dahl, Torsten Reuschel, Jan Birger Preibisch, Xiaomin Duan, Ivan Ndip, Klaus-Dieter Lang,
Christian Schuster
Efficient Total Crosstalk Analysis of Large Via Arrays in Silicon Interposers
IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no. 12, December 2016

Torsten Reuschel, J. Meischner
Ansatz zur Verbesserung des Vorstellungsvermögens elektromagnetischer Felder der Studierenden im Modul “Theoretische Elektrotechnik I: Zeitunabhängige Felder”
Praxisprojekte des Qualifizierungsprogramms “Forschendes Lernen an der TUHH”, Ausgabe 2. Hamburg, Germany: Zentrum für Lehre und Lernen, Technische Universität Hamburg, Nov. 2016, pp.23-27.

Alexander Vogt, Torsten Reuschel, Heinz-Dietrich Brüns, Sabine Le Borne, Christian Schuster
On the Treatment of Arbitrary Boundary Conditions Using a Fast Direct H-Matrix Solver in MoM
IEEE Transactions on Antennas and Propagation, Vol. 64, no.8, August 2016

Torsten Reuschel, Miroslav Kotzev, David Dahl, Christian Schuster
Modeling of Differential Striplines in Segmented Simulation of Printed Circuit Board Links
IEEE Signal and Power Integrity Conference (SIPI 2016), Ottawa, ON, Canada, July 25-29, 2016

David Dahl, Torsten Reuschel, Xiaomin Duan, Ivan Ndip, Klaus-Dieter Lang, Christian Schuster
On the Upper Bound of Total Uncorrelated Crosstalk in Large Through Silicon Via Arrays
IEEE Workshop on Signal and Power Integrity (SPI), Turin, Italy, May 8-11, 2016

Jan Birger Preibisch, Torsten Reuschel, Katharina Scharff, Christian Schuster
Impact of Continuous Time Linear Equalizer Variability on Eye Opening of High-Speed Links
IEEE Transactions on Electromagnetic Compatibility, vol. 58, no. 1, Februar 2016

Torsten Reuschel, Sebastian Müller, Christian Schuster
Segmented Physics-Based Modeling of Multilayer Printed Circuit Boards Using Stripline Ports
IEEE Workshop on Signal and Power Integrity (SPI), Turin, Italy, May 8-11, 2016

Young H. Kwark, Torsten Reuschel, Renato Rimolo-Donadio, Dierk Kaller, Thomas-M. Winkel, Hubert Harrer,
Christian Schuster
Systematic Analysis of Electrical Link Bottlenecks and Strategies for Their Equalization
DesignCon, Santa Clara, CA, USA, 19. -21. Januar 2016.

Sebastian Müller, Torsten Reuschel, Renato Rimolo-Donadio, Young H. Kwark, Heinz-D. Brüns, Christian Schuster
Energy-Aware Signal Integrity Analysis for High-Speed PCB Links
IEEE Transactions on Electromagnetic Compatibility, vol.57, no.5, Oktober 2015

Torsten Reuschel, Sebastian Müller, Heinz-D. Brüns, Christian Schuster
Investigation of Long Range Differential Crosstalk on Printed Circuit Boards
IEEE Workshop on Signal and Power Integrity (SPI), Ghent, Belgium, May 11-14, 2014

Electromagnetic Modeling and Optimization of Through Silicon Vias

Ph. D. Thesis David Dahl. 01.10.2012 – 13.12.2017

This thesis presents the simulation and the design of vertical interconnects in silicon substrates known as through silicon vias (TSVs) which are applied as a component of 3D integration of integrated circuits. Numerical methods of comparably high efficiency are developed and applied in order to simulate the electromagnetic properties of large realistic arrays of TSVS. The proposed methods are correlated with alternative methods and parameter variations are carried out to derive design guidelines. Further, several test structures with TSV are developed and the measurement results are correlated with the results from electromagnetic simulations.

Picture

A physics-based via model assuming metallic boundaries on top and bottom of the interposer structure. The near field effects are modeled by lumped capacitances while wave propagation in the cavity constituted by the substrate and the enclosing metallic layers is represented by the “parallel plate impedance”. (Source: TET, TUHH).

Picture

Schematic layout of a part of a silicon interposer where Through Silicon Vias (TSV) establish a connection between top and bottom of the structure. The metallic barrels of typically circular cross-section are electrically isolated from the conductive silicon substrate material by a thin silicon dioxide layer. Two principle types of wave propagation are investigated. (Source: TET, TUHH).

Related Publication:

David Dahl, Ivan Ndip, Klaus-Dieter Lang, Christian Schuster
Effect of 3D Stack-Up Integration on Through Silicon Via Characteristics
IEEE Workshop on Signal and Power Integrity (SPI), Lake Maggiore (Baveno), Italy, May 7-10, 2017

David Dahl, Torsten Reuschel, Jan Birger Preibisch, Xiaomin Duan, Ivan Ndip, Klaus-Dieter Lang,
Christian Schuster
Efficient Total Crosstalk Analysis of Large Via Arrays in Silicon Interposers
IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no. 12, Dezember 2016

Torsten Reuschel, Miroslav Kotzev, David Dahl, Christian Schuster
Modeling of Differential Striplines in Segmented Simulation of Printed Circuit Board Links
IEEE Signal and Power Integrity Conference (SIPI 2016), Ottawa, ON, Canada, July 25-29, 2016

Xiaomin Duan, Mathias Boettcher, David Dahl, Christian Schuster, Christian Tschoban, Ivan Ndip, Klaus-Dieter Lang
High Frequency Characterization of Silicon Substrate and through Silicon Vias
Electronic Components and Technology Conference (ECTC), Las Vegas, NV, US, May 31 – June 3, 2016

David Dahl, Torsten Reuschel, Xiaomin Duan, Ivan Ndip, Klaus-Dieter Lang, Christian Schuster
On the Upper Bound of Total Uncorrelated Crosstalk in Large Through Silicon Via Arrays
IEEE Workshop on Signal and Power Integrity (SPI), Turin, Italy, May 8-11, 2016

Xiaomin Duan, David Dahl, Ivan Ndip, Klaus-Dieter Lang, Christian Schuster
A Rigorous Approach for the Modeling of Through-Silicon-Via Pairs Using Multipole Expansions
IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no. 1, Januar 2016

Xiaomin Duan, David Dahl, Christian Schuster, Ivan Ndip, Klaus-Dieter Lang
Efficient Analysis of Wave Propagation for Through-Silicon-Via Pairs using Multipole Expansion Method
IEEE Workshop on Signal and Power Integrity (SPI), Berlin, Germany, May 10-13, 2015

Andreas Hardock, David Dahl, Heinz-Dietrich Brüns, Christian Schuster
Efficient Calculation of External Fringing Capacitances for Physics-Based PCB Modeling
IEEE Workshop on Signal and Power Integrity (SPI), Berlin, Germany, May 10-13, 2015

David Dahl, Xiaomin Duan, Ivan Ndip, Klaus-Dieter Lang, Christian Schuster
Efficient Computation of Localized Fields for Through Silicon Via Modeling Up to 500 GHz
IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 5, no. 12, Dezember 2015

David Dahl, Sebastian Müller, Christian Schuster
Effect of Layered Media on the Parallel Plate Impedance of Printed Circuit Boards
IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium, India, Bangalore, December 14-16, 2014

David Dahl, Anne Beyreuther, Xiaomin Duan, Ivan Ndip, Klaus-Dieter Lang, Christian Schuster
Analysis of Wave Propagation along Coaxial Through Silicon Vias Using a Matrix Method
IEEE Workshop on Signal and Power Integrity (SPI), Ghent, Belgium, May 11-14, 2014

David Dahl, Xiaomin Duan, Anne Beyreuther, Ivan Ndip, Klaus-Dieter Lang, Christian Schuster
Applying a physics-based via model for the simulation of Through Silicon Vias
IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, USA, October 27-30, 2013

David Dahl, Xiaomin Duan, Anne Beyreuther, Ivan Ndip, Klaus-Dieter Lang, Christian Schuster
Application of the Transverse Resonance Method for Efficient Extraction of the Dispersion Relation of Arbitrary Layers in Silicon Interposers
IEEE Workshop on Signal and Power Integrity (SPI), Paris, France, May 12-15, 2013

Software-Benchmarking for Signal and Power Integrity Applications

Industry Project. 01.03.2012 – 31.12.2014

The Institute of Electromagnetic Theory is evaluating SPEAG’s SEMCAD software, a FDTD based field solver, with respect to typical problems in signal and power integrity design of digital systems. Schmid & Partner Engineering AG (SPEAG) is a Zurich based company that develops and manufactures advanced numerical tools and instrumentation for evaluation of electromagnetic near- and far-fields from static to optical frequencies. SPEAG focuses on evaluation and optimization of EM fields in complex environments such as close to and within the human body. Typical applications include EM safety and design optimization of mobile phones, MRI, and medical implants.

Below is a benchmark from electronic packaging: A ball grid array (BGA) socket model consisting of approx. 28 million cells. Reflection, transmission, and crosstalk parameters were extracted in the frequency domain up to 40 GHz from time domain data. It can be seen that the crosstalk reaches a maximum in the frequency range from 10 to 15 GHz.


Picture1

SEMCAD model of ball grid array socket


Picture 2

S-parameters obtained from SEMCAD simulations

A second benchmark is the silicon interposer below with a pair of through silicon vias (TSVs) consisting of about 1 million cells. Results from time domain simulation using two digital pulses for excitation are shown. It can be seen that the TSVs shows mostly inductive reflection and produce crosstalk during rise and fall times.


Picture 3

SEMCAD model of silicon interposer with through silicon vias


Picture 4

Time domain results from SEMACD simulation

50+ Gbps High Speed Serial Link Design for Digital Systems

Industry Project. 01.08.2014 – 31.10.2014

High speed serial link design for digital systems is rapidly approaching the 25-50 Gbps data rate and is likely to move beyond in the next decade as can be seen e.g. from the recent 56 Gbps Common Electrical Interface (CEI) initiative of the Optical Internetworking Forum (OIF). With the increase in data rate problems in the areas of signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC) will exacerbate and require more attention than before in order to achieve a system that is not threatened in its electrical integrity (see figure below).
In this research project the Institute of Electromagnetic Theory was investigating on behalf of HUAWEI Research Europe the state of the art, the technical issues, and the necessary steps for electrical integrity at such advanced data rates. Specifically the following research areas were addressed in detail

– basic elements of successful link design methodologies,
– necessary CAD tools for link design,
– specific problems and challenges at 50+ Gbps signaling,
– suitable packaging & interconnect structures for 50+ Gbps signaling,
– most important research areas in the near future.

The results were summarized in a White Paper and presented at HUAWEI.

The concept of electrical integrity for digital systems: Typically, three aspects of electrical integrity are distinguished (left): power integrity, signal integrity, and electromagnetic compatibility. Although the three aspects have different objectives and use different methodologies, they are closely interlinked. The schematic at the right side of the figure illustrates the target domains of the different aspects, which can roughly be described as follows: Power integrity is concerned with providing a noise free power supply, signal integrity is concerned with the quality of signal transmission, and the electromagnetic compatibility is concerned with mitigating electromagnetic interference.

Via Array Modeling for Application in Fast, Energy-Efficient Digital Systems

Ph. D. Thesis Sebastian Müller. 01.04.2010 – 31.07.2014

This thesis studies the application of physics-based via models for an efficient modeling of large via arrays in multiglayer PCBs. Three main aspects are addressed: the study and improvement of the modeling accuray, the study and improvement of the model efficiency, and the application of the model in a systematic evaluation of via array design alternatives for high speed links.

With regard to the modeling accuracy, the application of an improved local field model is identified as a suitable way to improve the model accuraxy for the simulation of via arrays, especially at frequencies above 20 GHz. With the improved model, an accurate simulation of via arrays with a pitch of 60 mil or larger becomes possible in the frequency range up to 50 GHz. Improvements with regard to the model efficiency lead to a reduction of calculation times which allows to carry out fast design explorations for smaller via arrays on a stadard PC. Finally, an approach for the systematic design ebaluation is presented which intefrates the adventages of the efficient physics-based via model in a larger concept. With the approach, a quantitative comparison of design alternatives bevomes possible that takes into account the impact of design changes on both signal integrity and energy efficiency for the complete system.


Picture PCB Interconnect

(Source: TET, TUHH).


Picture Via Modell

(Source: TET, TUHH).

Related Publications:

Sebastian Müller, Xiaomin Duan, Christian Schuster
Energy-aware analysis of electrically long high speed I/O links
Computer Science – Research and Development, vol 29, no. 2, May 2014

Sebastian Müller
Correction to Complete modeling of large via constellations in multylayer printed circuit boards
IEEE Transactions on Components, Packaging and Manufacturing Tevchnology, vol 4, no. 4, April 2014

Sebastian Müller, Heinz-D. Brüns, Christian Schuster
Einfluss der Routinglage in Via-Arrays auf die Signalqualität bei hohen Datenraten
EMV Düsseldorf, Internationale Fachmesse und Kongress für Elektromagnetische Verträglichkeit, Düsseldorf; Germany, March 11-13, 2014

Sebastian Müller, Torsten Reuschel, Renato Rimolo-Donadio, Young H. Kwark,Heinz-D. Brüns, Christian Schuster
Energy-aware signal integrity analysis for high-speed PCB links
submitted to IEEE Transactions on Electromagnetic Compatibility, 2014

Sebastian Müller, Andreas Hardock, Renato Rimolo-Donadio, Heinz-Dietrich Brüns, Christian Schuster
Analytical Extraction of Via Near-Field Coupling Using a Multiple Scattering Approach
IEEE Workshop on Signal and Power Integrity (SPI), Paris, France, May 12-15, 2013

Sebastian Müller, Fabian Happ, Xiaomin Duan, Renato Rimolo-Donadio, Heinz-Dietrich Brüns, Christian Schuster
Complete Modeling of Large Via Constellations in Multilayer Printed Circuit Boards
IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 3, no. 3, March 2013

Sebastian Müller, Xiaomin Duan, Miroslav Kotzev, Yao-Jiang Zhang, Jun Fan, Xiaoxiong Gu, Young Kwark, Renato Rimolo-Donadio, Heinz-Dietrich Brüns, Christian Schuster
Accuracy of Physics-Based Via Models for Simulation of Dense Via Arrays
IEEE Transactions on Electromagnetic Compatibility, vol. 54, no. 5, October 2012

Sebastian Müller, Renato Rimolo-Donadio, Xiaomin Duan, Heinz-D. Brüns, Christian Schuster
Analytical Calculation of Conduction and Displacement Current Contributions in PCB Return Current Paths
Asia-Pacific EMC Symposium (APEMC), Singapore, May 21-24, 2012

Sebastian Müller, Renato Rimolo-Donadio, Heinz-Dietrich Brüns, Christian Schuster
Anwendung quasianalytischer Via-Modelle zur schnellen Simulation dichter Via-Arrays
Internationale Fachmesse und Kongress für Elektromagnetische Verträglichkeit, Düsseldorf; Germany, February 7-9, 2012

Sebastian Müller, Xiaomin Duan, Renato Rimolo-Donadio, Heinz-Dietrich Brüns, Christian Schuster
Recent Developments of Via and Return Current Path Modeling (Invited)
International Conference on Electromagnetics in Advanced Applications (ICEAA), Torino, Italy, September 12-16, 2011

Sebastian Müller, Xiaomin Duan, Renato Rimolo-Donadio, Heinz-D. Brüns, Christian Schuster
Non-Uniform Currents on Vias and Their Effects in a Parallel-Plate Environment
IEEE Electrical Design of Advanced Package & Systems Symposium (EDAPS), Singapore, December 7 – 9, 2010

Sebastian Müller, Renato Rimolo-Donadio, Heinz-D. Brüns, Christian Schuster
Effect of Mixed-Reference Planes on Single-Ended and Differential Links in Multilayer Substrates
IEEE Workshop on Signal Propagation on Interconnects (SPI), Hildesheim, Germany, May 9-12, 2010

Sebastian Müller, Renato Rimolo-Donadio, Heinz-D. Brüns, Christian Schuster
Schnelle Simulation verlustbehafteter Verbindungsstrukturen auf Leiterplatten auf der Grundlage quasianalytischer Via-Modelle und der Leitungstheorie
Internationale Fachmesse für elektromagnetische Verträglichkeit (EMV Düsseldorf) March 09.-11., 2010

Sebastian Müller
Including multiconductor transmission lines in a quasi-analytical model for multilayer structures
Diplomarbeit

Exploration of Power Supply Noise Effects on Maximum Data Rates of High Speed Digital Links in Advanced Server Systems

Industry Project. 18.06.2010 – 17.06.2013

High speed digital links in IBM’s server systems today are running at data rates of up to 10 Gigabit per second (Gbps). These links are crucial for the overall performance of the system and are carefully designed with respect to signal integrity and bit error rates. The design process follows an iterative procedure in which I/O circuit designers and package designers collectively optimize the link performance using appropriate models for each element of the communication system. As data rates increase in next generation platforms to exceed 12 Gbps, the fundamental noise coupling mechanisms will change making a localized nearest neighbour analysis less relevant. Newer architectures are also increasingly relying on differential links to provide a measure of noise rejection. Increasing data rates will involve new noise coupling mechanisms, many of which are increasingly sensitive to skew, power supply noise, and return current path discontinuities.

picture supercomputer

IBM Watson Supercomputer based on Power7 (Source: IBM)

picture transistors

Transistors on IBM Power6 Chip (Source: IBM)

The design process for high speed digital links is nowadays focused on the assessment of signal interconnect performance. Power delivery network design is usually a separate effort and its implications for signal quality and maximum achievable data rates are not routinely studied or accurately quantified. In this joint research project the Institute of Electromagnetic Theory in close collaboration with a team from IBM Germany Research & Development explored the effect of power supply noise on the maximum achievable data rates in IBM’s high speed digital links. The team developed successfully a power delivery model for packaging structures and a method for inclusion of simultaneous switching noise into the link budget simulation.

picture

Simulated eye diagram for a high speed digital link

Picture

Simulated eye diagram subject to power supply noise

Related Publications

R. Rimolo-Donadio, X. Duan, Y. Kwark, X. Gu, C. Baks, S. Müller, T.-M. Winkel, T. Strach, L. Shan, H. Harrer,
C. Schuster
Signal and Power Integrity (SPI) Co-Analysis for High-Speed Communication Channels
UBM DesignCon Conference, Santa Clara, CA, USA, January 28 – 31, 2013

T.-M. Winkel, H. Harrer, T. Strach, R. Rimolo-Donadio, Y. Kwark, X. Duan, C. Schuster
Framework for Co-Simulation of Signal and Power Integrity in Server Systems
IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Tempe, AZ, USA,
October 21-24, 2012

D. Timmermann, R. Rimolo-Donadio, Y. Kwark, T.-M. Winkel, C. Siviero, H. Harrer, C. Schuster
Methods for Calculation of Eye Diagrams for Digital Links with Multiple Aggressors Having Unknown Time Offsets
IEEE Workshop on Signal and Power Integrity (SPI), Sorrento, Italy, May 13-16, 2012

C. Schuster and R. Rimolo-Donadio
Modeling of Power Supply Noise Effects on High Speed Interconnects
Workshop on Power and Signal Integrity Co-Design for High-Speed Circuits (WS7), IEEE Asia-Pacific
EMC Symposium (APEMC), Melbourne, Australia, May 20-23, 2013

Development, Validation and Application of Semi-Analytical Interconnect Models for Efficient Simulation of Multilayer Substrates

Ph. D. Thesis Renato Rimolo-Donadio. 01.11.2006 – 31.12.2010

This project deals with the efficient modeling and simulation of multilayer substrates in high-speed electronic systems.
Semi-analytical models for vias and traces in packages and printed circuit boards are proposed and incorporated into a framework for automatic simulation of multilayer structures. The models are validated with general-purpose numerical methods for electromagnetic simulation and measurements, using typical configurations such as differential and single-ended links. Application scenarios of realistic complexity for signal integrity, power integrity, and electromagnetic compatibility are evaluated and the co-simulation of these three domains is explored.

TUHH Universitätsbibliothek. TUBDok Link:
http://doku.b.tu-harburg.de/volltexte/2011/1091


Picture

(Source: TET, TUHH).


Picture

(Source: TET, TUHH).

Related Publications:

Renato Riomolo-Donadio
Development, Validation, and Application of Semi-analytical Interconnect Models for Efficient Simulation of Multilayer Substrates.
Dissertation 2010. Logos Verlag Berlin. 2011 (ISBN 978-3-8325-2776-1)

Xiaoxiong Gu, Renato Rimolo-Donadio, Zhenwei Yu, Franceso de Paulis, Young H. Kwark, Matteo Cocchini, Mark B. Ritter, Bruce Archambeault, Albert Ruehli, Jun Fan, Christian Schuster
Fast-Physics-Based Via and Trace Models for Signal and Power Integrity Co-Analysis
IEC DesignCon Conference, Santa Carla, USA, Feb. 1-4, 2010

Renato Rimolo-Donadio, Xiaomin Duan, Heinz-D. Brüns, Christian Schuster
Comprehensive Multilayer Substrate Models for Co-Simulation of Power and Signal Integrity
IMAPS 42th International Symposium on Microelectronics and Packaging, San Jose, California, USA, November 3-5, 2009

Renato Rimolo-Donadio, Heinz-D. Brüns, Christian Schuster
Hybrid Approach for Efficient Calculation of the Parallel-Plate
Impedance of Lossy Power/Ground Planes
Microwave and Optical Technology Letters, Vol. 51, No. 9, September 2009

Renato Rimolo-Donadio, Xiaoxiong Gu, Young H. Kwark, Mark B. Ritter, Bruce Archambeault, Francesco De Paulis, Yaojiang Zhang, Jun Fan, Heinz-D. Brüns, and Christian Schuster
Physics-Based Via and Trace Models for Efficient Link Simulation on Multilayer Structures up to 40 GHz
IEEE Transactions on Microwave Theory and Techniques, Vol. 57, No. 8, August 2009

Renato Rimolo-Donadio, Xiaomin Duan, Heinz-D. Brüns, Christian Schuster
Differential to Common Mode Conversion Due to Asymmetric Ground Via Configurations
IEEE Workshop on Signal Propagation on Interconnects (SPI), Strasbourg, France, May 12-15, 2009

Yaojiang Zhang, Renato Rimolo-Donadio, Christian Schuster, Erping Li, Jun Fan
Extraction of Via-Plate Capacitance of an Eccentric Via by an Integral Approximation Method
IEEE Microwave and Wireless Components Letters, Vol. 19, No. 5, May 2009

Dong G. Kam, Mark B. Ritter, Troy J. Beukema, John F. Bulzacchelli, Petar K. Pepeljugoski, Young H. Kwark, Lei Shan, Xiaoxiong Gu, Christian W. Baks, Richard A. John, Gareth Hougham, Christian Schuster, Renato Rimolo-Donadio, Boping Wu.
Is 25 Gb/s On-Board Signaling Viable?
IEEE Transactions on Advanced Packaging, Vol. 32, No. 2, May 2009.

Xiaoxiong Gu, Francesco De Paulis, Renato Rimolo-Donadio, Ketan Shringarpure, Yaojiang Zhang, Bruce Archambeault, Sam Connor, Young H. Kwark, Mark B. Ritter, Jun Fan, Christian Schuster
Fully Analytical Methodology for Fast End-to-End Link Analysis on Complex Printed Circuit Boards including Signal and Power Integrity Effects.
IEC DesignCon Conference, Santa Clara, USA, February 2-5, 2009

Renato Rimolo-Donadio, Heinz-D. Brüns, Christian Schuster
Including Stripline Connections into Network Parameter Based Via Models for Fast Simulation of Interconnects
International Zurich Symposium on Electromagnetic Compatibility, Switzerland, Jan. 12-15, 2009

Mark B. Ritter, Petar Pepeljugoski, Xiaoxiong Gu, Young Kwark, Dong Kam, Renato Rimolo-Donadio, Boping Wu, Christian Baks, Richard John, Lei Shan, Christian Schuster
The Viability of 25 Gb/s On-board Signaling
IEEE Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, USA, May 27-30, 2008

Renato Rimolo-Donadio, Andrzej J. Stepan, Heinz-D. Brüns, James L. Drewniak, Christian Schuster
Simulation of Via Interconnects Using Physics-Based Models and Microwave Network Parameters
IEEE Workshop on Signal Propagation on Interconnects (SPI), Avignon, France, May 12-15, 2008

Renato Rimolo-Donadio, Christian Schuster, Young Kwark, Xiaoxiong Gu, Mark Ritter
Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects
IEEE Design, Automation and Test in Europe Conference and Exhibition DATE’08, Munich, Germany, March 10-14, 2008